1. Field of the Invention
The present invention relates to a field emission display (FED) and fabrication method thereof, and more specifically to a triode-type field emission display (FED) having a grid plate with spacer structure and fabrication method thereof.
2. Description of the Related Art
With the wide application of integrated circuits (ICs), various semiconductor devices with higher efficiency and lower cost are produced based on different objectives. DRAM is important in the information and electronics industry, with memory capacity a key characteristic thereof.
Most DRAM has one transistor and one capacitor per DRAM cell. Memory capacity of the DRAM has reached 256, and even 512 MB. Therefore, with increased integration, reduced size of memory cell and transistor is important in manufacture of DRAM with higher memory capacity and higher processing speed. 3-D capacitors such as a deep trench capacitor can itself reduce footprint on the semiconductor substrate, and thus, is applied to fabrication of the DRAM of 512 MB and above. A traditional plane transistor covers considerable area of the semiconductor substrate, creating problems for integration. Therefore, vertical transistors are becoming popular for fabrication of memory units. One of the most used DRAM cell arrays integrates vertical transistors with trench capacitors.
Nevertheless, as the size of elements is continuously reduced, so is trench storage node capacitance of DRAM. As a result, storage capacitance must be increased to maintain performance. Even though the storage capacitance can be increased by increasing the depth of the deep trench capacitor, finite depth limits the high aspect ratio capacitor process.
Currently, the method for increasing storage capacitance for DRAMs increases the width of the bottom of the trench, thereby increasing surface area to form a bottle-shaped trench capacitor.
FIGS. 1a to 1c are cross-sections illustrating the conventional process flow for forming a bottle trench. First, referring to FIG. 1a, a patterned pad layer 12 is formed on a silicon substrate 10. Then, the patterned pad layer 12 is used as an etching mask to etch the silicon substrate 10 by dry etching to form a trench 14 containing an upper portion 16 of width 13 and a lower portion 18.
Next, referring to FIG. 1b, a photoresist layer 22 covering the lower portion 18 of the trench 14 is formed. Subsequently, a sacrificial layer 20 covering the upper portion 16 of the trench 14 and the pad layer 12 is deposited. Then, referring to FIG. 1c, the photoresist layer 22 and the sacrificial layer 20 from the pad layer 12 are later removed by anisotropic etching. As a result, a residual sacrificial layer 21 is formed in the upper portion 16 of the trench 14.
Finally, referring to FIG. 1d, the silicon substrate 10 uncovered by the residual sacrificial layer 21 of the lower portion 18 of the trench 14 is etched by isotropic etching using ammonia and diluted hydrogen fluoride to form the lower portion 24 of the bottle shaped trench 17. The lower portion 24 is wider (at width 15) than the upper portion 16 (at width 13).
It is difficult to control the shape of the lower portion 22 of the trench 14 by the above method, which results in increased instability and difficulty during the fabricating process.
Therefore, a manufacturing process of trench capacitor with increased storage capacitance, in which trench depth and bottom width are not increased, is called for.